FIG. 1 illustrates a prior art memory module 10. The module includes memory devices 14 that are mounted on a circuit board 12 and connected to a computer memory system through an interface 18. The module may be, for example, a dual inline memory module (DIMM) in which the memory devices are dynamic random access memory (DRAM) devices mounted on a printed circuit board (PCB) and the interface 18 simply includes two rows of conductive contacts 20 on either side of the PCB to form a card edge connection between the module and a memory controller on a computer mother board.
A signal routing scheme 22 determines how the memory devices communicate with other components in the memory system. For example, memory devices 14 may be connected in a bus arrangement in which an individual signal line is directly connected between a contact 20 and more than one memory device. This may also be referred to as a multi-drop or star arrangement. Memory devices may also be connected in a point-to-point (P2P) arrangement in which an individual signal line only connects a contact with a single memory device. Additional point-to-point signal lines may also be used to connect the memory device to other memory devices. This may also be referred to as a daisy chain arrangement, and if the point-to-point connections allow for a closed loop, it may be referred to as a ring arrangement.
In some memory modules, the interface 18 may include additional functionality. For example, with a registered DIMM (RDIMM), the interface includes registers for the command and address signals, while the data lines are generally connected directly to the channel. In a fully buffered DIMM (FB-DIMM), all signal lines for the memory device, including the data lines, are buffered from the channel.
Memory devices on a module may be arranged in logical stacks 16 in which there is some overlap in the signaling to access different devices in the same stack as shown in FIG. 1. For example, on a dual-rank DIMM, one memory device may be physically stacked on top of another memory device with all terminals on the top device (rank 1) connected directly to the corresponding terminals on the bottom device (rank 0), except the chip select (CS) terminals CS0,CS1 are wired separately so that the ranks can be accessed separately. Memory devices may also be arranged in logical stacks even if the devices are not physically stacked. For example, two memory devices may have all of their corresponding terminals (except for the CS terminals) connected together through PCB traces even though both memory devices are mounted directly to the board. This may be referred to as a planar design even though the PCB may be flexible and not strictly planar, or the memory devices may be mounted on opposite sides of the board.